Semiconductor circuit, especially for ignition purposes, and the use of the same

ABSTRACT

A semiconductor circuit configuration is described, in particular for ignition applications, having a semiconductor power switching device which has a first main terminal, a second main terminal and a control terminal; a clamping diode device which is switched between the first main terminal and the control terminal for clamping an external voltage (V A ) which is applied at the first main terminal; the clamping diode device having a first part with a first clamp voltage and a second part with a second clamp voltage (V KL ′), the second part being connected in series with the first part; a controllable semiconductor switching device which is connected in parallel with the first part for controllable bridging of the first part, so that either the sum (V KL ) of the first and the second clamp voltages, or the second clamp voltage (V KL ′) is provided for clamping the external voltage (V A ) applied at the first main terminal; and a control circuit for controlling the controllable semiconductor switching device as a function of a predetermined operating state of the semiconductor power switching device.

This application is a 371 of PCT/DE02/0370009 filed on Sep. 30, 2002.

FIELD OF THE INVENTION

The present invention relates to a semiconductor circuit configuration,in particular for ignition applications.

BACKGROUND INFORMATION

Although it is also applicable to other similar semiconductorcomponents, the present invention as well as the problems on which it isbased are explained here with regard to a vertical IGBT (insulated gatebipolar transistor) for ignition applications.

IGBTs are used in general as power switching devices in the range of ablocking voltage of a few hundred volts up to a few thousand volts. Inparticular, the use of such IGBTs as ignition transistors, i.e., asswitches on the primary side of an ignition coil, is of particularinterest.

The structure of a vertical IGBT is similar to that of a VDMOStransistor, with the difference that a p⁺-emitter is situated on itsanode side instead of an n⁺-substrate as in the VDMOS transistor. GermanPatent No. 31 10 230 describes a vertical MOSFET component having thebasic structure of a vertical IGBT.

In principle, two types of vertical IGBT or V-IGBT are differentiated,namely a punch-through IGBT (PT) and a non-punch-through IGBT (NPT), asdescribed by Laska et al., Solid-State Electronics, volume 35, no. 5,pp. 681–685, for example.

The basic properties of these two types of IGBTs are described belowwith reference to FIG. 6.

FIG. 6 shows a schematic cross-sectional diagram of a known PT-IGBT orNPT-IGBT, labeled in general with reference number 100.

A PT-IGBT is usually produced on a thick p⁺-doped substrate having anepitaxially applied n⁻-buffer layer 140 and an n⁻-drift region 104,which is also applied epitaxially. For the smallest possible conductingstate voltage drop, the thickness of n⁻-drift region 104 is selected tobe smaller than required by the width of the space charge region inn⁻-drift region 104 at the desired blocking ability, so n-buffer layer140 has the function of preventing punch-through of the space chargeregion to rear p⁺-emitter 105 which is provided in the substrate. Toachieve a rapid shutdown of the electric current despite a goodp⁺-emitter 105, the carrier lifetime is kept small by lifetime killing,e.g., by radiation, and/or the doping of n-buffer layer 140 is selectedto be high accordingly. Since the conducting state voltage becomesgreater with an increase in the doping dose of n-buffer layer 140, agood compromise between conducting-state behavior and shutdown behavioris to be achieved with a thin, highly doped n-buffer layer 140.

An NPT-IGBT is derivable from the PT-IGBT by omitting n-buffer layer 140and selecting a greater thickness for drift region 104 than thatrequired by the width of the space charge region at the desired blockingability. The NPT-IGBT is usually produced on a low-doped substratehaving a high charge carrier lifetime, whereby after introducing thediffusion profiles on the front side of the wafer, a shallow p⁺-emitter105 having a depth of penetration of only a few μm (much less than 20μm) and a poor emitter efficiency is produced on the rear side of thewafer. Such a transparent p⁺-emitter 105 is used to ensure a rapidshutdown of the current in dynamic operation of the component with thegoal of minimizing shutdown losses. To achieve satisfactory conductingstate properties despite the poor p⁺-emitter 105, the carrier lifetimein n⁻-drift region 104 must be selected to be as high as possible, andfurthermore, the thickness of n⁻-drift region 104 is to be selected tobe as low as possible, taking into account the desired blocking abilityof the component.

On the front side, a PT-IGBT or NPT-IGBT is composed of an active region130 and an edge termination region 150, the latter ensuring the desiredblocking ability with respect to the edge of the chip. Active region 130is composed of a plurality of cell-shaped or strip-shaped MOS controlheads 106, 107, 108 connected in parallel. These MOS control heads 106,107, 108 are explained in greater detail below in conjunction with thefunctioning of vertical IGBTs.

MOS control heads 106, 107, 108 are obtained by continued reflection ofthe half-cell on section AA′ shown between sections AA′ and BB′ in FIG.6. Magnetoresistive structures are conventionally used in edge area 150to achieve the desired blocking ability. These magnetoresistivestructures are usually composed of a cathode 101, designed as a metalmagnetoresistor, a polysilicon magnetoresistor 153 a, which iselectrically connected to the former via the third dimension (notshown), a metal plating 152 connected to an n⁺-channel stopper 155 and apolysilicon magnetoresistor 153 b, which is electrically connected tometal plating 152 via the third dimension (not shown). Also shown are afield oxide 159 and an intermediate dielectric 110, which, in additionto specific contacting, has the function of electrically insulating themetal plating plane from the polysilicon plane.

The functioning of an NPT-IGBT or PT-IGBT in the conducting state isexplained first in greater detail below.

A gate 103, which is usually made of polysilicon and is insulated fromthe semiconductor body by a thin gate oxide layer 109, is brought to apotential above the threshold voltage of MOS control heads 106, 107, 108with respect to cathode 101. Then an inversion channel is created on thesemiconductor surface beneath gate 103 in the area of p-body region 108,whereupon the semiconductor surface is in a state of accumulation in thearea of n-drift region 104. When there is a positive voltage on anode102 relative to cathode 101, electrons are injected into n⁻-drift region104 via n⁺-source region 106, the MOS channel thus influenced, and theaccumulation layer. Then p⁺-emitter 105 on the anode side injects holes,so that n⁻-drift region 104 is flooded by charge carriers and itsconductivity is increased in active region 130 and in adjacent portionsof edge termination 150. These portions are in high injection at theusual conducting state current densities. Therefore, an IGBT having ablocking ability of more than approx. 150–200 V is capable of carrying ahigher current density with a smaller voltage drop between the anode andcathode than a MOS transistor having the same breakdown voltage. In theconducting state, current flows from anode 102 to cathode 101. It iscarried by electrons, which are injected into n⁻-drift region 104 andflow out over p⁺-emitter 105 on the anode side to anode 102, and it isalso carried by holes, which are injected from the p⁺-emitter on theanode side into n⁻-drift region 104 and flow over p-regions 107, 108 tocathode 101.

In addition to the planar vertical IGBT structures discussed here, thereare also vertical IGBTs having a trench gate, where the gate is createdin the form of a trench in the semiconductor surface. In this regard,see I. Omura et al., ISPSD '97, Conf. Proc., pp. 217–200. Thefunctioning of these vertical IGBTs having a trench gate is completelysimilar to that of the structures described above, but they offer theadvantage of a lower conducting state voltage drop.

The functioning of the NPT-IGBT or PT-IGBT in the blocking case will bedescribed now. In the blocking case, gate 103 is brought to a voltagebelow the threshold voltage relative to cathode 101. If anode 102 isthen brought to a positive potential, the space charge region, which hasdeveloped at the boundary between p-body region 108 and n⁻-drift region104, expands almost exclusively into n⁻-drift region 104.

In the NPT-IGBT, the thickness of n⁻-drift zone 104 is greater than thewidth of the space charge region at a given maximum blocking ability ofthe component. This results in the triangular curve (dotted line) ofelectric field strength |E| along thickness direction y of thecomponent, as indicated in FIG. 6. The maximum of field strength |E|occurs in the area of MOS control heads 106, 107, 108.

In the PT-IGBT, the thickness of n⁻-drift zone 104 is selected to beless than the width the space charge region would have at a givenmaximum blocking ability of the component. To prevent the space chargeregion from running up onto rear p⁺-emitter 105, n-doped buffer layer140 is introduced here with the goal of preventing punch-through. Thisresults in the trapezoidal curve (solid line) of electric field strength|E| indicated in FIG. 6 along thickness direction y of the component.The maximum field strength also occurs here in the area of MOS controlheads 106, 107, 108.

FIG. 7 shows a conventional circuit topology in which a vertical IGBT100 according to FIG. 6 is used as the ignition transistor in theprimary circuit of an ignition coil for an internal combustion engine.For this use as an ignition transistor, a V-IGBT having a requiredblocking ability of approx. 400–600 V has been used in the past.

According to FIG. 7, V-IGBT 100 having main terminal 101 correspondingto the cathode, main terminal 102 corresponding to the anode and controlterminal 103 corresponding to the gate is connected to battery voltageV_(Bat) at node 210 via a primary winding of an ignition coil 211. Aspark plug 212, a protective resistor 214 of 1–2 kΩ and a diode 213 forsuppressing the starting spark are connected on the secondary windingside of ignition coil 211.

V-IGBT 100 is integrated into a circuit system 200 having terminal nodes201, 202 and 203. Terminal node 202 is connected directly to first mainterminal 102 of V-IGBT 100, and terminal node 203, which is at groundGND, is connected directly to second main terminal 101 of V-IGBT 100.

The additional circuit components within circuit system 200 have thefunction of triggering and clamping V-IGBT 100. Diode 204 has thefunction of protecting gate 103, which is connected to it, fromovervoltages. When conducting, diode 206 prevents current from flowingfrom control terminal 103 to main terminal 102, which is connected toterminal 152 via the semiconductor material of the V-IGBT. Resistors 207of 1 kΩ, for example, and resistors 208 of 10–25 kΩ, for example,determine the input resistance of circuit system 200 at terminal node201 for a control signal ST, and they also form the load of a clampingdiode device 205, which is usually designed as a clamping diode chainhaving a plurality of polysilicon Zener diodes polarized in the reversedirection. Elements 204, 205, 206, 207 and 208 are usually integratedmonolithically with the V-IGBT, diodes 204, 206, in addition to element205, being also normally made of polysilicon.

As outlined here, clamping diode device 205 is not connected directly tothe metal plating of anode 102 because it is on the bottom side of thechip and is not readily accessible. Instead, it is in contact with metalplating 152 of channel stopper 155 which has the same potential as anode102 up to a forward voltage. Circuit system 200 is directly operable bya control unit via terminal node 201. To do so, a control signal SThaving a positive voltage of 5 V, for example, is applied to terminalnode 201, whereupon a current rise is initiated by ignition coil 211.

At a certain point in time, the voltage on terminal node 201 is reducedto approx. 0 V, whereupon the voltage on metal plating 152 and on mainterminal 102 and thus on terminal node 202 rises steeply. The voltagerise is transformed up on the secondary side of ignition coil 211,resulting in an ignition spark on spark plug 212. Clamping diode chain205 has the function of limiting the voltage rise at main terminal 102to so-called clamp voltage V_(KL) of approx. 400 V to protect V-IGBT 100and the other circuit components of circuit system 200. This isimportant in the pulse case in particular.

A pulse case occurs when no ignition spark is generated, e.g., due to adetached ignition cable. Then circuit system 200 including V-IGBT 100must absorb the energy which would otherwise be converted into a spark.

FIG. 3 shows a schematic diagram of the time characteristic of theclamping of the anode voltage with conventional circuit system 200.

A time characteristic of voltage V_(A) at first main terminal 102, i.e.,on terminal node 202 is shown in FIG. 3 with dotted line 302. It isassumed here that the ignition switch was switched on for a certainperiod of time during t<0, so that at time t=0, a current of typically 7to 20 A is flowing through V-IGBT 100 and ignition coil 211. If V-IGBT100 is switched off at t=0 due to the reduction in the voltage oftriggering signal ST at terminal node 201 to 0 V, then ignition coil 211is still forcing the full current on it at first.

Then voltage V_(A) at first main terminal 102 rises steeply. Withoutvoltage limiting, voltage V_(A) at first main terminal 102 would thenrise to the breakdown value of V-IGBT 100 and would destroy it. This isprevented by clamping diode device 205 in that on reaching preselectedclamp voltage V_(KL) at time t_(r) (t_(r) typically amounts to a fewμs), gate 103 of V-IGBT 100 is triggered so sharply that it preventsclamp voltage V_(KL) at main terminal 102 from being exceeded.

If the case is not a pulse case but instead a standard operating caseaccording to solid-line curve 301 in FIG. 3, then voltage V_(A) at firstmain terminal 102 would collapse after approx. t₁–t_(r)=15 μs, and afteranother approx. 15 μs, it would generate the ignition spark on sparkplug 212 at t_(f). The result would be a conversion of the energy storedin ignition coil 211 during sparking period t₃–t_(f) in the combustionchamber, during which only the inversely transformed spark voltage ofapprox. V_(B)=30 V would be applied to first main terminal 102 for mostof the time period at the end of sparking period t₃–t_(f) voltage V_(A)at main terminal 102 would again drop to battery voltage V_(Bat)=14 V.

In the pulse case, represented by dotted-line curve 302 in FIG. 3,however, the high clamp voltage of approx. 400 V would persist untiltime t₄, and the current flowing through ignition coil 211 and V-IGBT100 would subsequently drop linearly over time until time t₄. At timet₄, the coil energy will have dissipated, i.e., been converted to heatin circuit system 200, and voltage V_(A) at terminal 102 will dropsteeply to battery voltage V_(Bat). Period of time t₄–t_(r) lasts only afew hundred μs, but this operating case nevertheless makes a high demandon the pulse strength of IGBT 100 due to the high power converted, andthis requirement is not always met to an adequate extent. In the worstcase this results in destruction of IGBT 100.

J. Yedinak et al. (ISPSD '98, Conf. Proc., pp. 399–402) show, using theexample of a PT-IGBT that failure occurs as follows. In the pulse case,the space charge region has included the entire n⁻-drift region 104.Electrons are injected via the MOS channel that has developed into then⁻-drift region 104 via a triggering of gate 103 controlled by clampingdiode 205, these electrons triggering rear p⁺-emitter 105. The componentbecomes very hot, in particular in the area of cathode 101, due to thehigh current density, the high electric field strength and theassociated high power loss in the area of MOS control heads 106, 107,108, whereupon an electron leakage current occurs from MOS control heads106, 107, 108. The electrons run toward anode 102 and notch upp⁺-emitter 105. They thus function like additional triggering of IGBT100.

To keep the voltage at the level of the clamp voltage, the triggering ofgate 103 is reduced accordingly via clamping diode chain 205. Undercertain operating conditions, the notch-up due to the thermally inducedelectron leakage current is so great that V-IGBT 100 is able to carrythe load current without gate notch-up. Its controllability is lost.Then the temperature and leakage current of the component continue torise. Finally, thermal direct feedback occurs and V-IGBT 100 isdestroyed. In an investigation of the dependence of the pulse strengthof V-IGBTs on the clamp voltage according to Z. J. Shen et al., IEEEElectron Device Letters, volume 21, no. 3, March 2000, pp. 119–122, itwas found that the pulse strength increases greatly with a decrease inclamp voltage. The reason for this is the reduction in the powerconverted in V-IGBT 100 due to the drop in clamp voltage; thereby themaximum temperature which occurs in the area of MOS control heads 106,107, 108 drops during a pulse case.

If we consider standard ignition systems in a motor vehicle, we findthat the clamp voltage in such a system is not freely selectable and inparticular is not significantly reducible. A significantly reduced clampvoltage would endanger reliable generation of the ignition spark.

An intelligent V-IGBT having current limiting and an over-temperaturecutoff is described by Z. J. Shen et al., PCIM '96, Conf. Proc., pp.11–16, where polysilicon diodes are used as the temperature sensor. Inthe on-state, the IGBT is shut down on reaching a certain thresholdtemperature due to the fact that the monolithically integrated controlcircuit reduces the gate voltage. However, this IGBT is not suitable foruse as an ignition transistor because it does not have any clamping. Inaddition, an overtemperature cutoff by reducing the gate voltage wouldbe counterproductive in the pulse case because it would renderineffective the clamping, which also intervenes via the gate voltage.

An object of the present invention is thus to create an improvedsemiconductor circuit configuration, in particular for ignitionapplications, having a semiconductor power switching device which ismore protectable in a pulse case.

SUMMARY OF THE INVENTION

The semiconductor circuit configuration according to the presentinvention, in particular for ignition applications, has the advantagethat the semiconductor power switching device is better protectable in apredefinable operating phase without reducing its clamp voltage inanother predefinable operating phase. The circuits required fortriggering the determination of the time phases according to the presentinvention may advantageously be monolithically integratable into thesemiconductor power circuit device.

The idea on which the present invention is based is that the clampingdiode device has a first part having a first clamp voltage and a secondpart having a second clamp voltage, the second part being connected inseries with the first part. In addition, a controllable semiconductorswitching device, which is connected in parallel with the first part, isprovided for controllable bridging of the first part, so that either thesum of the first and second clamp voltages, or the second clamp voltageis provided for clamping the external voltage applied at the first mainterminal. A control circuit is used to control the controllablesemiconductor switching device as a function of a predeterminedoperating state of the semiconductor power switching device.

According to a preferred refinement, the predetermined operating stateis an operating temperature of the semiconductor power switching device.

According to another preferred refinement, a temperature sensor isprovided for detecting the operating temperature of the semiconductorpower switching device, and the control circuit is designed so that ittriggers the semiconductor switching device for bridging when theoperating temperature of the semiconductor power switching deviceexceeds a predetermined temperature.

According to another preferred refinement, the predetermined operatingstate is a state which prevails after a predetermined time lag after achange in state of a control signal applied to the control terminal.

According to another preferred refinement, the control circuit has atiming element for detecting the time lag after the change in state andis designed so that it triggers the semiconductor switching device forbridging when the detected time lag exceeds the predetermined time lag.

According to another preferred refinement, the controllablesemiconductor switching device is a second NMOS transistor whose controlterminal is connected to the first main terminal across a resistancedevice and parts of the semiconductor chip.

According to another preferred refinement, a voltage converting deviceis provided between the control circuit and the controllablesemiconductor switching device, having a first NMOS transistor whosefirst main terminal is connected to the control terminal of the secondNMOS transistor across two diodes in antiserial connection, and thecontrol circuit is connected via its second terminal and controlterminal.

According to another preferred refinement, the semiconductor powerswitching device is a vertical IGBT having: a rear emitter region of asecond type of conduction, a drift region of the first type ofconduction and a rear anode contact as the first main terminal; anoptional buffer region between the drift region and the rear emitterregion; a front MOS control structure having a front source region and abody region which are introduced into the drift region, and a controlcontact as the control terminal, situated with insulation above the bodyregion and a portion of the drift region connected to it; a frontcathode contact which is connected to the front source region and thebody region; the clamping diode device, the semiconductor switchingdevice, and the control circuit being integrated on the front sidebetween an active region and an edge termination metal plating of thesemiconductor power switching device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic cross-sectional diagram of a semiconductorcircuit configuration for ignition applications according to a firstembodiment of the present invention.

FIG. 2 shows a schematic cross-sectional diagram of a control part andswitching part of the semiconductor circuit configuration for ignitionapplications according to a second embodiment of the present invention.

FIG. 3 shows a schematic diagram of the time characteristic of theclamping of the anode voltage of the semiconductor power switchingdevice in the usual semiconductor circuit configuration for ignitionapplications and in the embodiments of the present invention.

FIG. 4 shows a schematic cross-sectional diagram of an integratedcircuit for the semiconductor circuit configuration for ignitionapplications according to the embodiments of the present invention.

FIG. 5 shows a schematic top view of the integrated circuit for thesemiconductor circuit configuration for ignition applications accordingto the embodiments of the present invention.

FIG. 6 shows a schematic cross-sectional diagram of a known NPT-IGBT andPT-IGBT.

FIG. 7 shows a conventional circuit topology using a vertical IGBT asthe ignition transistor in the primary circuit of an ignition coil foran internal combustion engine.

DETAILED DESCRIPTION

The same reference numbers in the figures denote the same components orthose having the same function.

FIG. 1 shows a schematic cross-sectional diagram of a semiconductorcircuit configuration for ignition applications according to a firstembodiment of the present invention.

FIG. 1 shows in general a semiconductor circuit configuration 400 forignition applications according to the first embodiment having a specialcircuit 401 in the area of clamping diode device 205 a, 205 b, which isconnected via metal plating 152 between first main terminal 102 andcontrol terminal 103. FIG. 1 shows certain circuit nodes 404, 405, 406,407 to which reference will be made below.

Clamping diode device 205 a, 205 b has a first chain part 205 a having afirst clamp voltage between circuit nodes 404, 405 and a second chainpart 205 b having a second clamp voltage, second part 205 b beingconnected in series with first part 205 a.

In addition, a controllable semiconductor switching device 402 isconnected in parallel with first part 205 a and is provided forcontrollable bridging of first part 205 a, so that either the sum of thefirst and second clamp voltages or the second clamp voltage is providedfor clamping external voltage V_(A) applied to first main terminal 102.

A control circuit 403 is used for controlling controllable semiconductorswitching device 402 as a function of a predetermined operating state ofthe semiconductor power switching device in the form of V-IGBT 100.

In particular, a clamping response may be imparted to the circuit systemaccording to the present embodiment by this special wiring, asillustrated by dotted-line curve 303 in FIG. 3.

The essential idea in this first embodiment is to switch the clampvoltage at a point in time t₂>t_(f) after spark production from the highlevel of V_(KL)=400 V to a much lower level V_(KL)′. This lower clampvoltage V_(KL)′ is preferably above inversely transformed sparkingvoltage V_(B) so as not to interfere with the sparking process instandard operation. For example, a value of V_(KL)′=50 V would be areasonable value. The point in time t₂ is preferably selected to be assoon as possible after spark generation at time t_(f). The reduction inclamp voltage after the spark has been produced ensures reliable sparkproduction by retaining a high clamp voltage V_(KL) in the sparkgeneration phase, while on the other hand greatly reducing the powerloss in V-IGBT 100 and greatly reducing the heat generated in the pulsecase and thereby increasing its pulse strength. As shown clearly in FIG.3, the dissipation of the energy stored in ignition coil 211 is spreadover a larger interval of time, which ends at point in time t₅.

According to this embodiment, this behavior is achievable by the factthat clamping diode chain 205 according to FIG. 7, which is known perse, is divided into a high-blocking part 205 a having a breakdownvoltage of 350 V, for example, and a low-blocking part 205 b having abreakdown voltage of 50 V, for example, high-blocking part 205 a beingbridgeable with semiconductor switching device 402. When switchingdevice 402 is open, full clamp voltage V_(KL)=400 V prevails, and whenswitching device 402 is closed, a reduced clamp voltage V_(KL)′prevails.

The switching state of switching device 402 may be selected by asuitably designed control circuit 403 according to predeterminedcriteria. For example, in the first embodiment, temperature iscontrolled on the basis of the chip temperature using a temperaturesensor TS.

In the case of the temperature-controlled circuit version, switchingdevice 402 is initially open at t=0. When the chip temperature detectedby the temperature sensor exceeds a predetermined temperature valuebecause a pulse case is present, switching device 402 is closed bycontrol circuit 403, so the clamp voltage is reduced to voltage V_(KL)′by the end of the pulse case. This end may also be detected on the basisof the temperature, e.g., the temperature falling below a predeterminedtemperature value, or it may be defined automatically after apredetermined period of time has elapsed.

Temperature sensor TS, which is necessary for such atemperature-dependent control, may be formed by polysilicon diodes, forexample, whose temperature-dependent forward voltage is analyzed (see Z.J. Shen et al., PCIM '96, Conf. Proc., pp. 11–16). In addition, it isalso conceivable to analyze the temperature-dependent blocking currentof pn junctions or the temperature-dependent threshold voltage of MOStransistors used as temperature sensor TS. Temperature sensor TS ispreferably situated at the center of active region 130 because the chipis hottest there. If a certain temperature gradient is taken intoaccount, however, placement at a distance from the center of the chip,i.e., active region 130, is also possible with a suitable design of theanalysis in control circuit 403. The power supply of temperature sensorTS together with particular control circuit 403 may be derived, forexample, from the anode voltage or from circuit nodes 405, 406 accordingto the related art.

FIG. 2 shows a schematic cross-sectional diagram of control andswitching part 401 of the semiconductor circuit configuration forignition applications according to a second embodiment of the presentinvention.

In the second embodiment, there is a time-controlled selection of theswitching state of switching device 402 according to FIG. 1, althoughthat is implemented here by NMOS transistor 650 having control terminal653, the additional circuit part outside of block 403 being a voltagelevel converter.

In general, switching device 402 is also open at time t=0 intime-controlled selection. Switching device 402 is closed and the clampvoltage is reduced to V_(KL)′ at a predetermined time t₂ after turningoff the voltage of triggering signal ST at terminal node 201 at t=0.

Special control circuit 403 according to FIG. 2 includes an RC timingelement composed of a resistor 510 and a capacitor 511, the latteroptionally being formed by a polysilicon electrode separated from thesemiconductor only by thin gate oxide 109. The RC timing element ischarged during time t<0 from the positive voltage of triggering signalST applied at terminal node 207 up to a maximum equal to the voltagedefined by diode 504 via diode 509 and decoupling resistor 514.

A first NMOS transistor 570 having a first and second main terminals 571and 572, respectively, and a control terminal 573 is switched on duringtime t<0. At time t=0, V-IGBT 100 is switched off by applying 0 V atterminal node 201. Circuit node 406 is then also at 0 V, and diode 509prevents a sudden discharge of the RC timing element, which is why firstNMOS transistor 570 remains turned on initially.

Due to the shutdown of the voltage at terminal node 201, voltage V_(A)at main terminal 102 increases up to high clamp voltage V_(KL) of 400 V.Approximately this clamp voltage V_(KL) is also applied to metal plating152 and consequently to circuit node 404, while approximately the lowerclamp voltage V_(KL)′ is applied at node 405 and at node 513. Thebreakdown voltage of diode 505 should therefore be selected to beidentical to that of second partial diode change 205 b. In addition,gate protective diodes 507 a, 507 b are to be provided for a second NMOStransistor 650 which is situated in the edge area of the IGBT chip andremains blocked initially.

Capacitor 511 of the RC timing element is subsequently discharged acrossresistor 510, which results in shutdown of first NMOS transistor 570 atpredetermined time t=t₂. Due to the current flow across polysiliconresistor 659, which has a high voltage strength and is situated in ameandering pattern in the V-IGBT edge area, for example, the voltage atnode 513 increases and notches up the second NMOS transistor 650. Sincethis corresponds to switch element 402 in FIG. 1, high-blocking part 205a of the clamping diode chain is then bridged, and consequently theclamp voltage is reduced to V_(KL)′.

In principle all the components used in the circuit system explainedhere according to the first and/or second embodiment are monolithicallyintegratable with V-IGBT 100.

FIG. 4 shows a schematic cross-sectional diagram of an integratedcircuit embodiment of the semiconductor circuit configuration forignition applications according to the embodiments of the presentinvention.

FIG. 4 shows in general an integrated circuit system 600 having anactive region 130, a logic circuit region 670 and an edge terminationregion 150′, n-buffer layer 140 being optional.

The known edge termination having components 152, 153 b, 155 accordingto FIG. 6 is supplemented by the addition of high voltage resistantpolysilicon meandering resistor 659, and second NMOS transistor 650according to FIG. 2.

Second NMOS transistor 650 has a source metal plating 651, which isequipped with a magnetoresistor and an associated polysilicon gate 653to achieve a high blocking ability. Also shown is an n⁺-source region656, a p⁺-contact diffusion 657, and a body region 658 on whose surface,which is situated beneath gate 653, an inversion channel may be created.

First NMOS transistor 570 is shown in the logic region having p-logictrough 577 situated between sections BB′ and CC′ as representative ofthe other components that may be shown. This transistor has a sourcemetal plating 571, an n⁺-source region 576, an n⁺-drain metal plating572, an n⁺-drain region 575 and a gate electrode 573. An associatedp-trough 577 is also shown.

To have a greater freedom in the wiring, n⁺-source region 576 iscontactable individually via source metal plating 521 and is notshort-circuited to p-trough 577. p-trough 577 is at the same potentialas cathode region 101, 107, 108 of the V-IGBT. It therefore capturesholes emitted by emitter 105 on the anode side. To ensure the mostinterference-free possible functioning of the logic, p-logic trough 577should be connected to cathode 101 via p⁺-contact diffusion 107 at thelargest possible number of points. According to an optimum embodiment,each individual NMOS transistor is enclosed completely in the form of aring with p⁺-contact diffusions and body diffusions 107, 108, which areconnected to 101, as diagramed in the cross section according to FIG. 4.

FIG. 5 shows a schematic top view of the integrated circuit of thesemiconductor circuit configuration for ignition applications accordingto the embodiments of the present invention.

In addition to the reference notation already introduced, FIG. 5 shows aregion 703 in which polysilicon diode chains 205 a, 205 b, 505 and 506are situated. A metallic gate bond land 702 is connected electrically togate 103. A cathode bond land 701 is a partial region of the cathodemetal plating of cathode 101 in active portion 130 of the V-IGBT.

Although the present invention has been described above on the basis ofa preferred exemplary embodiment, it is not limited to this embodiment,but may instead be modified in a variety of ways.

Although the present invention has been explained on the example of aplanar n-channel PT-IGBT, it may be applied in principle to other powerswitching devices such as planar p-channel PT-IGBTs, planar NPT-IGBTs,trench PT-IGBTs, trench NPT-IGBTs, SPT-IGBTs, MOS transistors having aplanar gate or trench gate, etc.

If the types of doping and the sign of the voltage to be applied areswitched, for example, this yields a corresponding p-channel IGBT fromthe n-channel IGBT. In general, this version is superior to then-channel NPT-IGBT with regard to the latch-up strength but is inferiorwith regard to the avalanche strength.

Representation of RC timing elements having time constants in the μsrange is space intensive. An alternative which could also be integratedwould be to use a multivibrator having a downstream frequency divider,e.g., in NMOS resistance logic instead of the RC timing element in thecontrol circuit. The exemplary embodiments of switched clampingexplained above may also be refined in another embodiment not shownhere. To do so, the case in which it is impossible to generate severalsparks in series is considered. In this case of a longer pulse trainaccording to curve 303 in FIG. 3, the average power loss increases incomparison with a train of pulses according to curve 302 in FIG. 3. Toprevent the resulting damage in the structure and joining of the circuitsystem, a warning signal should therefore be generated by an additionallogic unit in this type of operation to suppress further output stagetriggering.

For example, at a time t, which is between time t₂ and time t₅, aninquiry may be made of node 405 or gate terminal 103 regarding thevoltage state. If the voltage state is above a certain threshold levelso that it indicates a pulse case according to curve 303 in FIG. 3, theneither the next positive triggering signal at node 406 may be suppresseddirectly or an entry may be made in an error counter which suppressesadditional positive triggering signals at node 406 only on reaching acertain number of pulses according to curve 303 in FIG. 3.

The required logic and the error counter which may also be required, mayalso be integrated monolithically in the usual manner and/or situatedexternally.

List of Reference Notation VS, RS front side, rear side AA′, BB′, CC′cross sections 102 anode terminal 101 cathode terminal 105 rearp⁺-emitter 140 n-buffer layer 104 n⁻-drift region 109 gate oxide 108p-body region 106 n⁺-source region 107 p⁺-contact region 103 gateterminal 110 intermediate dielectric 130 active region 150 edge area153a polysilicon magnetoresistor 153b polysilicon magnetoresistor 152metal plating 155 channel stopper 159 field oxide E field strength ythickness direction 200, 400 circuitry 201, 202, 203 terminal node 204,206 diodes 205 clamping diode chain 205a, 205b partial clamping diodechains 207, 208 resistors GND ground V_(A) voltage on 102 100 V-IGBT 210node for V_(Bat) 211 ignition coil 213 diode 214 resistor 212 spark plugST control signal 401 additional wiring 402 switching device 403 controlcircuit TS temperature sensor 404, 405, 406, 407 circuit node 514resistor 509, 504 diode 510, 511 RC timing element 570 first NMOStransistor 571, 572, 573 terminals of 570 505, 506, 507a/b, 508, diode512 513 node 650 second NMOS transistor 653 control terminal of 650 301,302, 303 clamping curves t time V_(B) feedback operating voltage V_(KL),V_(KL)′ clamp voltage 575, 576 source, drain of 570 577 p-trough of 570651 source metal plating of 650 657, 658 contact diffusion and body of650 656 source of 650 701 cathode bond land 702 gate bond land 703 diodechain region

1. A semiconductor circuit configuration, comprising: a semiconductorpower switching device that includes a first main terminal, a secondmain terminal, and a control terminal; a clamping diode device connectedbetween the first main terminal and the control terminal and forclamping an external voltage applied to the first main terminal, whereinthe clamping diode device includes: a first part possessing a firstclamp voltage, and a second part possessing a second clamp voltage andconnected in series to the first part; a controllable semiconductorswitching device connected in parallel to the first part for producing acontrollable bridging of the first part, so that one of the second clampvoltage and a sum of the first clamp voltage and the second clampvoltage is provided for clamping the external voltage; a control circuitfor controlling the controllable semiconductor switching device as afunction of a predetermined operating state of the semiconductor powerswitching device, wherein the predetermined operating state is anoperating temperature of the semiconductor power switching device; and atemperature sensor for detecting the operating temperature of thesemiconductor power switching device, wherein: the control circuittriggers the controllable semiconductor switching device when theoperating temperature exceeds a predetermined temperature.
 2. Thesemiconductor circuit configuration as recited in claim 1, wherein: thesemiconductor circuit configuration is for an ignition application. 3.The semiconductor circuit configuration as recited in claim 1, wherein:the predetermined operating state is a state that prevails after apredetermined time lag following a change in state of a control signalapplied at the control terminal.
 4. The semiconductor circuitconfiguration as recited in claim 3, wherein: the control circuitincludes a timing element for detecting a time lag after the change instate, and the control circuit triggers the controllable semiconductorswitching device when the time lag exceeds the predetermined time lag.5. A semiconductor circuit configuration, comprising: a semiconductorpower switching device that includes a first main terminal, a secondmain terminal, and a control terminal; a clamping diode device connectedbetween the first main terminal and the control terminal and forclamping an external voltage applied to the first main terminal, whereinthe clamping diode device includes: a first part possessing a firstclamp voltage, and a second part possessing a second clamp voltage andconnected in series to the first part; a controllable semiconductorswitching device connected in parallel to the first part for producing acontrollable bridging of the first part, so that one of the second clampvoltage and a sum of the first clamp voltage and the second clampvoltage is provided for clamping the external voltage; a control circuitfor controlling the controllable semiconductor switching device as afunction of a predetermined operating state of the semiconductor powerswitching device; and a resistance device, wherein: the controllablesemiconductor switching device includes a first NMOS transistor, and acontrol terminal of the first NMOS transistor is connected to the firstmain terminal across the resistance device.
 6. The semiconductor circuitconfiguration as recited in claim 5, further comprising: a voltageconverting device arranged between the control circuit and thecontrollable semiconductor switching device, wherein: the voltageconverting device includes a second NMOS transistor, a first mainterminal of the second NMOS transistor is connected to the controlterminal of the first NMOS transistor, and the control circuit isconnected via a second main terminal and a control terminal of thesecond NMOS transistor.
 7. A semiconductor circuit configuration,comprising: a semiconductor power switching device that includes a firstmain terminal, a second main terminal, and a control terminal; aclamping diode device connected between the first main terminal and thecontrol terminal and for clamping an external voltage applied to thefirst main terminal, wherein the clamping diode device includes: a firstpart possessing a first clamp voltage, and a second part possessing asecond clamp voltage and connected in series to the first part; acontrollable semiconductor switching device connected in parallel to thefirst part for producing a controllable bridging of the first part, sothat one of the second clamp voltage and a sum of the first clampvoltage and the second clamp voltage is provided for clamping theexternal voltage; and a control circuit for controlling the controllablesemiconductor switching device as a function of a predeterminedoperating state of the semiconductor power switching device; wherein thesemiconductor power switching device includes a vertical IGBT having: arear emitter region of a first type of conduction, a drift region of asecond type of conduction, a rear anode contact as the first mainterminal, an optional buffer region arranged between the drift regionand the rear emitter region, a front MOS control structure having: afront source region and a body region that are introduced into the driftregion, and a control contact as the control terminal that is situatedabove the body region and above a portion of the drift region adjacentthereto, the control contact being insulated, and a front cathodecontact that is connected to the front source region and the bodyregion, wherein the clamping diode device, the controllablesemiconductor switching device, and the control circuit are integratedon a front side between an active region and a metal edge-terminationplating of the semiconductor power switching device.